FloPoCo

Circuits computing just right

The best and most versatile free floating point unit out there is FloPoCo. (...) It outperforms even expensive professional solutions.

http://embdev.net/topic/215370

Version 3.0 is being released in 2015! See the release notes

A lot has been going on (transition to Sollya4, rewriting operators for bit-heaps, fixed-point support, ...). flopoco-3.0 is still beta, with a lot of operators broken by these framework changes. If you use it, please test each operator with the associated testbench generator (these can be trusted and checked!).

Get it from the InriaGForge page of the project or the one-line install for Ubuntu.

FPGA Arithmetic the way it should be

FloPoCo is a generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only).

The first motto of FloPoCo is that arithmetic on FPGAs should not mimick processor arithmetic. By designing radically new operators, one may obtain more accurate results with less hardware in less time. This thesis was first detailed in this document.

The second motto of FloPoCo is to enable computing just right. All FloPoCo operators are

  1. fully parameterized in precision, so that your application may use just the precision it needs, and
  2. accurate to the last bit, so that your wires don't carry meaningless noise.
Internally, FloPoCo operators are carefully designed to ensure that no bit is computed that is not useful to the final result.

FloPoCo is not a library of operators, but a generator of operators written in C++. It inputs operator specifications, and outputs synthesizable VHDL.

Distribution

FloPoCo is open-source. Contributions are welcome!

The intent of the authors is to distribute FloPoCo as free software (in the FSF AGPL sense), while imposing that the source code generated by FloPoCo is also free software (also AGPL-like). The (A)GPL doesn't seem to allow that, so it seems we have to invent something.

Current state of the license is therefore "all right reserved", which just means that the distribution terms are still being decided by the copyright owners (a consortium of the employers of the authors).

If this is a problem for your application, we are ready to negociate a commercial license: contact us.

Get it!

Installation instructions (including one-line install for Ubuntu) are provided in the user manual.

User manual

Developer manual


Selected publications related to FloPoCo

How to cite FloPoCo

If you want to refer to the framework, or the project as a whole, please cite publication [31] below.

If you want to refer to a specific operator, please cite the publication that describes it, if it exists. Otherwise [31] below.

For some slides, see a FloPoCo tutorial at HiPEAC 2013.

[41] Florent de Dinechin, Matei Istoan, and Abdelbassat Massouri. Sum-of-product architectures computing just right. In Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2014. [ bib | http | .pdf ]
[40] Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, and Bogdan Popa. Arithmetic core generation using bit heaps. In Field-Programmable Logic and Applications, September 2013. [ bib | .pdf ]
[39] Florent de Dinechin, Matei Istoan, and Guillaume Sergent. Fixed-point trigonometric functions on FPGAs. In Highly-Efficient Accelerators and Reconfigurable Technologies, March 2013. [ bib | .pdf ]
[38] Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, and Bogdan Pasca. Floating-point exponentiation units for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 2013. [ bib | http | .pdf ]
[37] Florent de Dinechin and Bogdan Pasca. High-Performance Computing using FPGAs, chapter Reconfigurable Arithmetic for High Performance Computing, pages 631-664. Springer, 2013. [ bib | .pdf ]
[36] Florent de Dinechin and Laurent-Stéphane Didier. Table-based division by small integer constants. In Applied Reconfigurable Computing, pages 53-63, Hong Kong, Hong Kong, March 2012. [ bib | http | .pdf ]
[35] Hong Diep Nguyen, Bogdan Pasca, Thomas B. Preußer. FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. Field Programmable Logic and Applications, 2011. [ .pdf ]
[34] Florent de Dinechin. Multiplication by rational constants. IEEE Transactions on Circuits and Systems, II, 2011. [ bib | http | .pdf ]
[33] Florent De Dinechin. The arithmetic operators you will never see in a microprocessor. In 20th IEEE Symposium of Computer Arithmetic, pages pp 189-190, Germany, July 2011. IEEE. [ bib | http ]
[32] Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco. An FPGA architecture for solving the Table Maker's Dilemma. In Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on, pages 187-194, Santa Monica, United States, 2011. IEEE Computer Society. Best paper award. [ bib | DOI | http ]
[31] Florent de Dinechin and Bogdan Pasca. Designing custom arithmetic data paths with FloPoCo. IEEE Design & Test of Computers, August 2011. [ pdf ]
[30] Mark G. Arnold and Sylvain Collange. A Real/Complex Logarithmic Number System ALU. In IEEE Transactions on Computers, 60(2):202-213, 2011.
[29] Florent de Dinechin and Bogdan Pasca. Floating-point exponential functions for DSP-enabled FPGAs. In Field Programmable Technologies, 2010. [ bib | http ]
[28] Florent de Dinechin, Mioara Joldes, and Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific Systems, Architectures and Processors. IEEE, 2010. [ bib | .pdf ]
[27] Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. In Highly-Efficient Accelerators and Reconfigurable Technologies, 2010. [ bib | .pdf ]
[26] Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Multiplicative square root algorithms for FPGAs. In Field-Programmable Logic and Applications, pages 574-577, 2010. [ bib | .pdf ]
[25] Florent de Dinechin, Hong Diep Nguyen, and Bogdan Pasca. Pipelined FPGA adders. In Field-Programmable Logic and Applications, pages 422-427, 2010. [ bib | .pdf ]
[24] Florent de Dinechin. A flexible floating-point logarithm for reconfigurable computers. Lip research report rr2010-22, ENS-Lyon, 2010. [ bib | http ]
[23] Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Racines carrées multiplicatives sur FPGA. In SYMPosium en Architectures nouvelles de machines (SYMPA), Toulouse, September 2009. [ bib | .pdf ]
[22] Florent de Dinechin, Cristian Klein, and Bogdan Pasca. Generating high-performance custom floating-point pipelines. In Field Programmable Logic and Applications. IEEE, August 2009. [ bib | .pdf ]
[21] Florent de Dinechin and Bogdan Pasca. Large multipliers with fewer DSP blocks. In Field Programmable Logic and Applications. IEEE, August 2009. [ bib | .pdf ]
[20] Mark G. Arnold and Sylvain Collange. A Dual-Purpose Real/Complex Logarithmic Number System ALU. In 19th Symposium on Computer Arithmetic. IEEE, June 2009. [ .pdf ]
[19] Ionut Trestian, Octavian Cret, Laura Cret, Lucia Vacariu, Radu Tudoran, and Florent de Dinechin. FPGA-based computation of the inductance of coils used for the magnetic stimulation of the nervous system. In Biomedical Electronics and Devices, volume 1, pages 151-155, 2008. [.pdf ]
[18] Jérémie Detrey and Florent de Dinechin. Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques, 27(6):673-698, 2008.
[17] Christoph Lauter and Florent de Dinechin. Optimising polynomials for floating-point implementation. In Real Numbers and Computers, pages 7-16, 2008. [.pdf ]
[16] Nicolas Brisebarre, Florent de Dinechin, and Jean-Michel Muller. Integer and floating-point constant multipliers for FPGAs. In Application-specific Systems, Architectures and Processors, pages 239-244. IEEE, 2008. [.pdf ]
[15] Florent de Dinechin, Bogdan Pasca, Octavian Cret, and Radu Tudoran. An FPGA-specific approach to floating-point accumulation and sum-of-products. In Field-Programmable Technologies, pages 33-40. IEEE, 2008. [.pdf ]
[14] Jérémie Detrey and Florent de Dinechin. A tool for unbiased comparison between logarithmic and floating-point arithmetic. Journal of VLSI Signal Processing, 49(1):161-175, 2007. [ .pdf ]
[13] Jérémie Detrey, Florent de Dinechin, and Xavier Pujol. Return of the hardware floating-point elementary function. In 18th Symposium on Computer Arithmetic, pages 161-168. IEEE, 2007. [ .pdf ]
[12] Jérémie Detrey and Florent de Dinechin. Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing, 31(8):537-545, 2007. [ .pdf ]
[11] Florent de Dinechin, Jérémie Detrey, Ionut Trestian, Octavian Cret, and Radu Tudoran. When FPGAs are better at floating-point than microprocessors. Technical Report ensl-00174627, École Normale Supérieure de Lyon, 2007. [ http ]
[10] Jérémie Detrey and Florent de Dinechin. Floating-point trigonometric functions for FPGAs. In Field-Programmable Logic and Applications, pages 29-34. IEEE, 2007. [ .pdf ]
[9] Florent de Dinechin. Matériel et logiciel pour l'évaluation de fonctions numériques. précision, performance et validation. Mémoire d'habilitation à diriger les recherches, 2007. [ .pdf ]
[8] Sylvain Collange, Jérémie Detrey, and Florent de Dinechin. Floating point or LNS: choosing the right arithmetic on an application basis. In 9th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD'2006), pages 197-203, Dubrovnik, Croatia, 2006. IEEE. [ .pdf ]
[7] Jérémie Detrey and Florent de Dinechin. Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Technique et science informatiques, 24(6):625-643, 2005.
[6] Florent de Dinechin and Arnaud Tisserand. Multipartite table methods. IEEE Transactions on Computers, 54(3):319-330, 2005. [ .pdf ]
[5] Jérémie Detrey and Florent de Dinechin. Table-based polynomials for fast hardware function evaluation. In Application-specific Systems, Architectures and Processors, pages 328-333. IEEE, 2005. [ .pdf ]
[4] Jérémie Detrey and Florent de Dinechin. A parameterizable floating-point logarithm operator for FPGAs. In 39th Asilomar Conference on Signals, Systems & Computers. IEEE, 2005. [ .pdf ]
[3] Jérémie Detrey and Florent de Dinechin. A parameterized floating-point exponential function for FPGAs. In Field-Programmable Technology. IEEE, 2005. [ .pdf ]
[2] Jérémie Detrey and Florent de Dinechin. Second order function approximation using a single multiplication on FPGAs. In 14th Intl Conference on Field-Programmable Logic and Applications (LNCS 3203), pages 221-230. Springer, 2004. [ .pdf ]
[1] Jérémie Detrey and Florent de Dinechin. A VHDL library of LNS operators. In 37th Asilomar Conference on Signals, Systems and Computers, 2003.

Authors and credits

FloPoCo is managed by Florent de Dinechin (contact: Florent.de-Dinechin at insa-lyon.fr).

Active developers: Nicolas Brunie, Fabrizio Ferrandi, Matei Istoan, Antoine Martinet, David Thomas.

Former developers: Sebastian Banescu, Sylvain Collange, Kinga Illyes, Cristian Klein, Mioara Joldes, Bogdan Pasca, Bogdan Popa, Xavier Pujol, Guillaume Sergent, Radu Tudoran, Alvaro Vasquez.

Much of FloPoCo's operator code is based on FPLibrary and HOTBM code by Jérémie Detrey.

The following people have contributed to FloPoCo in some sort or some other: Greg Davey, Mariusz Grad, Daniele Mastrandrea, Pedro Echeverría Aramendi.

FloPoCo uses Sollya, developed by Christoph Lauter, Sylvain Chevillard and Mioara Joldes. It also relies on GMP and MPFR.

FloPoCo is essentially developed using Free Software. Special thanks to the GHDL project for providing us a perfectly useable VHDL simulator that we can use when we are away from our ModelSim license servers.

The following support is gratefully acknowledged