Publications using FloPoCo

If some of your works belong there, please drop a mail to F. de Dinechin with the corresponding bibtex entries


[39] François Serre and Markus Püschel. A DSL-based FFT hardware generator in scala. In International Conference on Field Programmable Logic and Application (FPL). IEEE, 2018. [ bib ]
[38] Georgios Chatzianastasiou and George A. Constantinides. An efficient FPGA-based axis-aligned box tool for embedded computer graphics. In International Conference on Field Programmable Logic and Application (FPL). IEEE, 2018. [ bib ]
[37] Björn Liebig, Julian Oppermann, Oliver Sinnen, and Andreas Koch. Improved high-level synthesis for complex CellML models. In Applied Reconfigurable Computing. Architectures, Tools, and Applications, pages 420--432. Springer, 2018. [ bib ]
[36] Alberto A Del Barrio, Roman Hermida, and Seda Ogrenci-Memik. A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. IEEE Transactions on Circuits and Systems I: Regular Papers, pages 1--14, 2018. [ bib ]
[35] I Petrousov and M Dasygenis. Realization of a hardware generator for the sum of absolute difference component. Modern Circuits and Systems ..., pages 1--4, 2017. [ bib ]
[34] Martin Langhammer and Bogdan Pasca. Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs. IEEE Transactions on Computers, 66(12):2031--2043, 2017. [ bib ]
[33] Ting Yu, Chris Bradley, and Oliver Sinnen. ODoST: Automatic hardware acceleration for biomedical model integration. Transactions on Reconfigurable Technology and Systems, 9(4):27:1--27:24, August 2016. [ bib | DOI ]
[32] Ovidiu Sicoe and Mircea Popa. Generation of floating point 2d scaling operators for fpga. In 11th IEEE International Symposium on Applied Computational Intelligence and Informatics, May 2016. [ bib ]
[31] Ting Yu, Julian Oppermann, Chris Bradley, and Oliver Sinnen. Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models. Concurrency and Computation: Practice and Experience, 28(5):1480--1506, 2016. [ bib ]
[30] Ayan Palchaudhuri and Rajat Subhra Chakraborty. High Performance Integer Arithmetic Circuit Design on FPGA, volume 51 of Springer Series in Advanced Microelectronics. Springer India, New Delhi, 2016. [ bib ]
[29] Razvan Nane, Vlad-Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Brown, Fabrizio Ferrandi, Jason Anderson, and Koen Bertels. A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 35(10):1591--1604, 2016. [ bib ]
[28] Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, and Stanislav Sedukhin. Stream computation of shallow water equation solver for FPGA-based 1D tsunami simulation. In Highly-Efficient Accelerators and Reconfigurable Technologies, June 2015. [ bib ]
[27] Ayan Palchaudhuri, Rajat Subhra Chakraborty, and Durga Prasad Sahoo. Automated Design of High Performance Integer Arithmetic Cores on FPGA. 2015 Euromicro Conference on Digital System Design (DSD), pages 322--329, 2015. [ bib ]
[26] Joseph Tarango, Eamonn Keogh, and Philip Brisk. Accelerating the dynamic time warping distance measure using logarithmic arithmetic. In 48th Asilomar Conference on Signals, Systems and Computers, November 2014. [ bib ]
[25] Kentaro Sano, Hayato Suzuki, Ryo Ito, Tomohiro Ueno, and Satoru Yamamoto. Stream processor generator for HPC to embedded applications on FPGA-based system platform. In International Workshop on FPGAs for Software Programmers, pages 43--48, September 2014. [ bib ]
[24] Aryan Tavakkoli and David B. Thomas. Low-latency option pricing using systolic binomial trees. In Field-Programmable Technologies, 2014. [ bib ]
[23] Martin Langhammer and Bogdan Pasca. Faithful single-precision floating-point tangent for FPGAs. In FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, page 39, New York, New York, USA, February 2013.  ACM Request Permissions. [ bib ]
[22] Joseph Tarango, Eamonn Keogh, and Philip Brisk. Instruction set extensions for dynamic time warping. In Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. IEEE, 2013. [ bib | http ]
[21] Joseph Tarango, Eamonn Keogh, and Philip Brisk. Instruction set extensions for dynamic time warping. In International Conference on Hardware/Software Codesign and System Synthesis, 2013. [ bib ]
[20] David B. Thomas and Hideharu Amano. A fully pipelined FPGA architecture for stochastic simulation of chemical systems. In Field-Programmable Logic and Applications, 2013. [ bib ]
[19] Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Kyo Koizumi, and Satoru Yamamoto. Efficient custom computing of fully-streamed lattice Boltzmann method on tightly-coupled FPGA cluster. ACM SIGARCH Computer Architecture News, 41(5):47--52, 2013. [ bib ]
[18] Nachiket Kapre. Exploiting input parameter uncertainty for reducing datapath precision of spice device models. In Field-Programmable Custom Computing Machines, pages 189--197. IEEE, 2013. [ bib ]
[17] X Gao and S Bayliss. SOAP: Structural optimization of arithmetic expressions for high-level synthesis. ... Technology (FPT), pages 112--119, 2013. [ bib ]
[16] Björn Liebig, Jens Huthmann, and Andreas Koch 0001. Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis. IPDPS Workshops, pages 134--143, 2013. [ bib ]
[15] Christian Pilato and Fabrizio Ferrandi. Bambu: A modular framework for the high level synthesis of memory-intensive applications. In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL), pages 1--4. IEEE, 2013. [ bib ]
[14] Yoshiaki Kono, Kentaro Sano, and Satoru Yamamoto. Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation. In Field-Programmable Logic and Applications (FPL2012), August 2012. [ bib ]
[13] Hélene Martorell and Nachiket Kapre. FX-SCORE: a framework for fixed-point compilation of SPICE device models using gappa++. In Field-Programmable Custom Computing Machines, pages 77--84. IEEE, 2012. [ bib ]
[12] Christophe Alias, Bogdan Pasca, and Alexandru Plesco. Automatic generation of fpga-specific pipelined accelerators. In Applied Reconfigurable Computing, March 2011. [ bib ]
[11] Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco. An FPGA architecture for solving the Table Maker's Dilemma. In Application-Specific Systems, Architectures and Processors (ASAP), pages 187--194, Santa Monica, United States, 2011. IEEE. Best paper award. [ bib | DOI | .pdf ]
[10] Mark G. Arnold and Sylvain Collange. A real/complex logarithmic number system ALU. IEEE Transactions on Computers, 60(2):2012--213, 2011. [ bib ]
[9] Hong Diep Nguyen, Bogdan Pasca, and Thomas B Preußer. FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. In International Conference on Field Programmable Logic and Applications (FPL), pages 232--237. IEEE, 2011. [ bib ]
[8] Florent de Dinechin, Honoré Takeugming, and Jean-Marc Tanguy. A 128-tap complex FIR filter processing 20 giga-samples/s in a single FPGA. In 44th Asilomar Conference on Signals, Systems & Computers, 2010. [ bib | .pdf ]
[7] Mark G. Arnold and Sylvain Collange. A dual-purpose real/complex logarithmic number system ALU. In 19th Symposium on Computer Arithmetic. IEEE, 2009. [ bib | .pdf ]
[6] David B. Thomas and Wayne Luk. Estimation of sample mean and variance for Monte-Carlo simulations. In Field-Programmable Technologies, pages 89--96, 2008. [ bib | .pdf ]
[5] Octavian Cret, Ionut Trestian, Radu Tudoran, Laura Darabant, Lucia Vacariu, and Florent de Dinechin. Accelerating the computation of the physical parameters involved in transcranial magnetic stimulation using FPGA devices. Romanian Journal of Information, Science and Technology, 10(4):361--379, 2008. [ bib ]
[4] Ionut Trestian, Octavian Cret, Laura Cret, Lucia Vacariu, Radu Tudoran, and Florent de Dinechin. FPGA-based computation of the inductance of coils used for the magnetic stimulation of the nervous system. In Biomedical Electronics and Devices, volume 1, pages 151--155, 2008. [ bib | .pdf ]
[3] Jérémie Detrey and Florent de Dinechin. A tool for unbiased comparison between logarithmic and floating-point arithmetic. Journal of VLSI Signal Processing, 49(1):161--175, 2007. [ bib | DOI | .pdf ]
[2] Sylvain Collange, Jérémie Detrey, and Florent de Dinechin. Floating point or LNS: choosing the right arithmetic on an application basis. In 9th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD'2006), pages 197--203, Dubrovnik, Croatia, 2006. IEEE. [ bib | DOI | .pdf ]
[1] Jérémie Detrey and Florent de Dinechin. Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Technique et science informatiques, 24(6):625--643, 2005. [ bib ]

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