Publications about FloPoCo

If some of your works belong there, please drop a mail to F. de Dinechin with the corresponding bibtex entries


[43] Florent de Dinechin and Matei Istoan. Hardware implementations of fixed-point Atan2. In 22nd Symposium of Computer Arithmetic. IEEE, June 2015. [ bib | .pdf ]
[42] David B. Thomas. A general-purpose method for faithfully rounded floating-point function approximation in FPGAs. In 22d Symposium on Computer Arithmetic. IEEE, 2015. [ bib | .pdf ]
[41] Florent de Dinechin, Matei Istoan, and Abdelbassat Massouri. Sum-of-product architectures computing just right. In Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2014. [ bib | http | .pdf ]
[40] Martin Kumm and Peter Zipf. Efficient High Speed Compression Trees on Xilinx FPGAs. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014. [ bib ]
[39] Martin Kumm and Peter Zipf. Pipelined Compressor Tree Optimization Using Integer Linear Programming. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 1--8. IEEE, 2014. [ bib ]
[38] Konrad Möller, Martin Kumm, Marco Kleinlein, and Peter Zipf. Pipelined reconfigurable multiplication with constants on FPGAs. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 1--6. IEEE, 2014. [ bib ]
[37] Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, and Bogdan Popa. Arithmetic core generation using bit heaps. In Field-Programmable Logic and Applications, September 2013. [ bib | .pdf ]
[36] David B. Thomas. Parallel generation of gaussian random numbers using the table-hadamard transform. In FPGAs for custom computing machines, 2013. [ bib | .pdf ]
[35] Florent de Dinechin, Matei Istoan, and Guillaume Sergent. Fixed-point trigonometric functions on FPGAs. SIGARCH Computer Architecture News, 41(5):83--88, 2013. [ bib | .pdf ]
[34] Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, and Bogdan Pasca. Floating-point exponentiation units for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 2013. [ bib | http | .pdf ]
[33] Florent de Dinechin and Bogdan Pasca. High-Performance Computing using FPGAs, chapter Reconfigurable Arithmetic for High Performance Computing, pages 631--664. Springer, 2013. [ bib | .pdf ]
[32] Florent de Dinechin and Laurent-Stéphane Didier. Table-based division by small integer constants. In Applied Reconfigurable Computing, pages 53--63, Hong Kong, March 2012. [ bib | .pdf ]
[31] Florent de Dinechin. Multiplication by rational constants. IEEE Transactions on Circuits and Systems, II, 52(2):98--102, February 2012. [ bib | http | .pdf ]
[30] Martin Kumm, Katharina Liebisch, and Peter Zipf. Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 255--261, 2012. [ bib ]
[29] Martin Kumm and Peter Zipf. Hybrid Multiple Constant Multiplication for FPGAs. In IEEE International Conference on Electronics, Circuits and Systems, (ICECS), pages 556--559, 2012. [ bib ]
[28] Bogdan Mihai Pasca. High-performance floating-point computing on reconfigurable circuits. Theses, Ecole normale supérieure de lyon - ENS LYON, September 2011. [ bib | http | .pdf ]
[27] Florent de Dinechin and Bogdan Pasca. Designing custom arithmetic data paths with FloPoCo. IEEE Design & Test of Computers, 28(4):18--27, July 2011. [ bib | .pdf ]
[26] Florent de Dinechin. The arithmetic operators you will never see in a microprocessor. In 20th Symposium on Computer Arithmetic, pages pp 189--190. IEEE, July 2011. [ bib | .pdf ]
[25] Hong Diep Nguyen, Bogdan Pasca, and Thomas B. Preu├čer. FPGA-specific arithmetic optimizations of short-latency adders. In Field Programmable Logic and Applications. IEEE, 2011. [ bib | http ]
[24] Alvaro Vazquez and Florent de Dinechin. Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. In Field-Programmable Technology, pages 126--133, December 2010. [ bib | .pdf ]
[23] Florent de Dinechin and Bogdan Pasca. Floating-point exponential functions for DSP-enabled FPGAs. In Field Programmable Technologies, pages 110--117, December 2010. [ bib | .pdf ]
[22] P. D. Vouzis, Sylvain Collange, and Mark G. Arnold. A novel cotransformation for LNS subtraction. Journal of Signal Processing Systems, 58(1):29--40, 2010. [ bib ]
[21] Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. ACM SIGARCH Computer Architecture News, 38:73--79, 2010. [ bib | http | .pdf ]
[20] Florent de Dinechin. A flexible floating-point logarithm for reconfigurable computers. Lip research report rr2010-22, ENS-Lyon, 2010. [ bib | http ]
[19] Florent de Dinechin, Mioara Joldes, and Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific Systems, Architectures and Processors. IEEE, 2010. [ bib | .pdf ]
[18] Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. In Highly-Efficient Accelerators and Reconfigurable Technologies, 2010. [ bib | .pdf ]
[17] Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Multiplicative square root algorithms for FPGAs. In Field-Programmable Logic and Applications, pages 574--577, 2010. [ bib | .pdf ]
[16] Florent de Dinechin, Hong Diep Nguyen, and Bogdan Pasca. Pipelined FPGA adders. In Field-Programmable Logic and Applications, pages 422--427, 2010. [ bib | .pdf ]
[15] Florent de Dinechin, Cristian Klein, and Bogdan Pasca. Generating high-performance custom floating-point pipelines. In Field Programmable Logic and Applications, pages 59--64. IEEE, August 2009. [ bib | .pdf ]
[14] Florent de Dinechin and Bogdan Pasca. Large multipliers with fewer DSP blocks. In Field Programmable Logic and Applications, pages 250--255. IEEE, August 2009. [ bib | .pdf ]
[13] Nicolas Brisebarre, Florent de Dinechin, and Jean-Michel Muller. Integer and floating-point constant multipliers for FPGAs. In Application-specific Systems, Architectures and Processors, pages 239--244. IEEE, 2008. [ bib | .pdf ]
[12] Florent de Dinechin, Bogdan Pasca, Octavian Cret, and Radu Tudoran. An FPGA-specific approach to floating-point accumulation and sum-of-products. In Field-Programmable Technologies, pages 33--40. IEEE, 2008. [ bib | .pdf ]
[11] Jérémie Detrey and Florent de Dinechin. Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques, 27(6):673--698, 2008. [ bib ]
[10] Florent de Dinechin. Matériel et logiciel pour l'évaluation de fonctions numériques. Précision, performance et validation. PhD thesis, 2007. [ bib | .pdf ]
[9] Florent de Dinechin, Jérémie Detrey, Octavian Cret, and Radu Tudoran. When FPGAs are better at floating-point than microprocessors. Technical Report ensl-00174627, ÉNS Lyon, 2007. http://prunel.ccsd.cnrs.fr/ensl-00174627. [ bib ]
[8] Jérémie Detrey and Florent de Dinechin. Floating-point trigonometric functions for FPGAs. In Field-Programmable Logic and Applications, pages 29--34. IEEE, 2007. [ bib | .pdf ]
[7] Jérémie Detrey, Florent de Dinechin, and Xavier Pujol. Return of the hardware floating-point elementary function. In 18th Symposium on Computer Arithmetic, pages 161--168. IEEE, 2007. [ bib | .pdf ]
[6] Jérémie Detrey and Florent de Dinechin. Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing, 31(8):537--545, 2007. [ bib | DOI | .pdf ]
[5] Jérémie Detrey. Arithmétiques réelles sur FPGA : virgule fixe, virgule flottante et système logarithmique. PhD thesis, École Normale Supérieure de Lyon, Lyon, France, January 2007. [ bib | .pdf ]
[4] Florent de Dinechin and Arnaud Tisserand. Multipartite table methods. IEEE Transactions on Computers, 54(3):319--330, 2005. [ bib | .pdf ]
[3] Jérémie Detrey and Florent de Dinechin. Table-based polynomials for fast hardware function evaluation. In Application-specific Systems, Architectures and Processors, pages 328--333. IEEE, 2005. [ bib | .pdf ]
[2] Jérémie Detrey and Florent de Dinechin. A parameterizable floating-point logarithm operator for FPGAs. In 39th Asilomar Conference on Signals, Systems & Computers. IEEE, 2005. [ bib | .pdf ]
[1] Jérémie Detrey and Florent de Dinechin. A parameterized floating-point exponential function for FPGAs. In Field-Programmable Technology. IEEE, 2005. [ bib | .pdf ]

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